This invention relates to buses used for carrying information between functional blocks of an electronic circuit and, more particularly, to electronic circuits which utilize dynamic bus partitioning for reduced power consumption. The invention is typically utilized for improving the operation of high speed circuitry on a single monolithic substrate, but is not limited to such use.
In state of the art processors, the use of on-chip memory and wide internal buses has become an increasingly common approach to solving the throughput bottleneck associated with moving data on and off a chip. This trend, combined with very long instruction word architectures and high operating frequencies, has caused the capacitance and power consumption of on-chip buses to increase dramatically.
As used herein, the term xe2x80x9cbusxe2x80x9d refers to a set of electrical conductors, typically multiple conductors, used for carrying electrical signals between two or more circuits. The bus may be a data bus, an address bus, a control bus or any other type of bus. The electrical signals may represent data, addresses, control information, instructions, operands or any other type of information. The bus is typically an internal bus on a monolithic integrated circuit, known as an xe2x80x9con-chipxe2x80x9d bus.
A digital signal processor architecture that utilizes three 128-bit data buses is disclosed in U.S. Pat. No. 5,896,543 issued Apr. 20, 1999 to Garde. The data buses interconnect three memory banks, two computation blocks, a control block and an external port. The clock rate of the data buses may be 166 Megahertz or greater. It may be shown that three 128-bit data buses operating at a frequency of 250 Megahertz dissipate 1.5 watts when it is assumed that each bus conductor has a capacitance of 5 picofarads. The size and complexity of such a digital signal processor architecture dictate a large chip and therefore relatively long bus lengths and high capacitance. The higher capacitance contributes to increased power dissipation and reduces the maximum operating frequency. Furthermore, in devices having buses with a large number of bits, it is not always possible to simply make each conductor wider to increase the speed of the bus, as this would cause the bus to be unacceptably large. The bus would also consume far too much power, since the power of the bus grows linearly with the width of the bus conductors.
A technique for reducing power dissipation in large datapaths is disclosed by H. Kapadia et al. in xe2x80x9cReducing Switching Activity on Datapath Buses with Control-Signal Gatingxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 34, No. 3, March 1999, page 405-414. The disclosed technique involves control signal gating. When a bus is not used in a datapath, it is held in a quiescent state by stopping the propagation of switching activity through the module driving the bus. The disclosed technique involves the use of multiplexers in the datapath. This approach has the disadvantage that the multiplexers can add significantly to the delay of the datapath.
Accordingly, there is a need for improved techniques for reducing power dissipation and capacitance on high speed buses.
According to a first aspect of the invention, electronic apparatus is provided. The electronic apparatus comprises a plurality of functional electronic blocks, a bus interconnecting the functional blocks, one or more electronically controllable switches partitioning the bus into bus segments and a switch controller. Each of the electronically controllable switches has an on state wherein two of the bus segments are interconnected and an off state wherein the two bus segments are isolated. The switch controller controls the states of the electronically controllable switches in response to control information, such as information representative of the source and the destination of each bus transaction.
In a preferred embodiment, the functional blocks are components of a digital signal processor and may be fabricated on a single substrate.
The switch controller may include a source-destination decoder for controlling the states of the electronically controllable switches in response to control information representative of the source and the destination of each bus transaction. The switch controller may dynamically change the states of the electronically controllable switches between transactions of a sequence of bus transactions. In another embodiment, the switch controller may control the states of the electronically controllable switches to permit two or more bus transactions to be performed simultaneously.
According to another aspect of the invention, a method is provided for communicating between functional blocks in electronic apparatus comprising a plurality of functional electronic blocks interconnected by a bus. The method comprises the steps of partitioning the bus into bus segments, enabling a bus transaction between a source functional block and a destination functional block by interconnecting bus segments to complete a connection between the source and destination functional blocks, and performing the bus transaction on the interconnected bus segments.
According to a further aspect of the invention, electronic apparatus comprises a plurality of functional electronic blocks interconnected by a bus, means for partitioning the bus into bus segments, and means for enabling a bus transaction on the bus by interconnecting bus segments in response to control information representative of the source and the destination of the bus transaction.